Munich RISC-V First Meetup

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RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. […] Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. — About RISC-V Foundation

The Munich RISC-V First Meetup was last week. I had looked at RISC-V some time ago, but when Chris Lattner went to SiFive earlier this year, I took a closer look at RISC-V. Chris Lattner is known for LLVM, Clang, Swift, Xcode and other 😎 stuff.

The Meetup was great. Of course, there was a brief overview of RISC-V, including the Instruction Set Architecture (ISA) and Physical Memory Protection. A list of RISC-V books (see also RISC-V Books):

… and some lightning talks:


I am very enthusiastic about Renode, therefore I list a few points from the presentation and a few additional links I found:

… and Renode does not only simulate RISC-V processors.


It was an overall very well done meetup where I learned a lot. I have ordered a Sipeed Mix BiT and look into Renode. I am already curious about the 2nd Meetup. Thanks also to Andes Technology and the Munich University of Applied Sciences for supporting the Meetup.