RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. […] Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. — About RISC-V Foundation
The Munich RISC-V First Meetup was last week. I had looked at RISC-V some time ago, but when Chris Lattner went to SiFive earlier this year, I took a closer look at RISC-V. Chris Lattner is known for LLVM, Clang, Swift, Xcode and other 😎 stuff.
The Meetup was great. Of course, there was a brief overview of RISC-V, including the Instruction Set Architecture (ISA) and Physical Memory Protection. A list of RISC-V books (see also RISC-V Books):
- Computer Organization and Design RISC-V Edition: The Hardware Software Interface (Amazon, ISBN-13: 978-0128122754)
- The RISC-V Reader: An Open Architecture Atlas (Amazon, ISBN-13: 978-0999249116)
- Computer Architecture: A Quantitative Approach (Amazon, ISBN-13: 978-0128119051)
… and some lightning talks:
- Alexander Zeh about MiG-V: The First Logically Obfuscated 64-bit RISC-V Core For seL4
- Sven Beyer about Proving Your RISC-V Design Correct: OneSpin RISC-V Formal Verification completely verifies RISC-V Core RTL implementations with full proofs.
- A Universal Sensor Plattform (USeP) for IIoT and Edge Devices
- How to run Linux on RISC-V (see also FOSDEM’20) … on a $13 Sipeed MAix BiT
- Renode: an open source framework to scale the RISC-V
I am very enthusiastic about Renode, therefore I list a few points from the presentation and a few additional links I found:
- entire SoC complex, with I/O like USB, PCIe, CAN, I2C, SPI, GPIO, … (see also Microsemi Mi-V example)
- used by Amazon FreeRTOS team (see also AWS Announces RISC-V Support in the FreeRTOS Kernel and Using FreeRTOS on RISC-V Microcontrollers)
- potential for onboarding customers into FreeRTOS without hardware
- primary development platform, IDE integration
- Dornerworks seL4 porting used Renode to port to RISC-V (see also Using Renode To Build Secure Products On The seL4 Microkernel and RISC-V Architecture)
- Zephyr relies on Remonde for testing its TSN subsystem (see also Testing Zephyr PTP support)
… and Renode does not only simulate RISC-V processors.
It was an overall very well done meetup where I learned a lot. I have ordered a Sipeed Mix BiT and look into Renode. I am already curious about the 2nd Meetup. Thanks also to Andes Technology and the Munich University of Applied Sciences for supporting the Meetup.